AI Chip Packaging Pushes Beyond Reticle Limits, with CoWoS-L Set to Remain the Mainstream Advanced Packaging Solution Through 2028, Says TrendForce

TrendForce’s latest research into advanced semiconductor packaging reveals that GPU suppliers and hyperscale CSPs are continuing to develop increasingly powerful and versatile AI chips, making larger package sizes a key development priority for 2.5D packaging. Although TSMC’s CoWoS-L faces competition from Intel’s EMIB-T, its advantages in technology maturity and yield are expected to keep it the mainstream packaging solution for AI chips through 2028.

TrendForce notes that strong AI demand continues to support NVIDIA’s push toward integrated GB/VR rack-scale solutions, which incorporate large numbers of chips. NVIDIA’s high-end GPU shipments are expected to grow approximately 30% YoY in 2026. AMD, meanwhile, is aggressively promoting its MI400/MI450 series beginning in the second half of 2026, providing further momentum to overall shipments.

Google is expected to lead among CSP-developed ASICs in both shipment volume and growth momentum in 2026, with TPU v7 serving as its primary product. AWS is also expanding aggressively, with its chips and AI server systems gradually transitioning to Trainium v3 beginning in 2H26. Microsoft and Meta currently remain more heavily reliant on GPU servers, with comparatively smaller ASIC deployment plans.

Strong AI chip demand tightens TSMC packaging capacity, creating potential spillover opportunities for Intel EMIB-T

TrendForce notes that AI server chips have mainly used TSMC’s CoWoS-S packaging, which employs a silicon interposer to connect HBM with compute dies, enabling the high performance needed for generative AI. 

However, as chip sizes grow and more HBM modules are added, manufacturing the silicon interposer is nearing its physical limits. Besides changing interposer materials, the industry needs to shift toward CoWoS-L solutions that allow for larger reticle-size exposures. CoWoS-L offers greater flexibility by embedding high-speed silicon (Si) bridge dies within the interposer, enabling better integration and interconnection between compute dies and HBM.

Specifically, CoWoS-S can integrate two SoCs/chiplets and eight HBM modules and is expected to remain in use for ASICs such as Microsoft’s Maia 200. Designs requiring greater numbers of SoCs/chiplets and HBM modules, however, will need to transition to CoWoS-L. NVIDIA and AMD AI accelerators have already adopted CoWoS-L. Among AI ASICs, Meta's MTIA 400 already uses CoWoS-L, while AWS and Microsoft are also expected to adopt CoWoS-L in 2027.

However, the larger interposer required by CoWoS-L raises packaging costs, while persistent constraints on TSMC’s packaging capacity have further increased interest in Intel’s EMIB technology as an alternative. By reducing reliance on costly large interposers, EMIB offers the potential for lower overall packaging costs, although its performance is constrained by the routing density of the package substrate. 

Intel has improved line/space (L/S) and microbump specifications to address this limitation, while developing more advanced solutions such as EMIB-T. By incorporating through-silicon vias (TSVs), EMIB-T shortens signal paths and enhances overall module performance.

TrendForce observes that Google is expected to adopt EMIB-T packaging in 2027, while AWS is also testing EMIB technology. Although EMIB-T competes directly with CoWoS-L, CoWoS-L’s advantages in technology maturity and yield are expected to keep it as the mainstream packaging technology for AI chips through 2028.