[News] Micron Reportedly Rules Out 4F² DRAM Scaling, Backs 6F² and 3D DRAM in Next-Gen Memory Roadmap

Micron is sticking with its 6F² DRAM architecture rather than adopting 4F², even as Chinese rival CXMT advances the alternative design. According to Nikkei, Scott DeBoer, Micron’s president and chief technology and products officer, said during a recent technology webinar that 4F² is not “on the roadmap right now” after more than 20 years of evaluation. Instead, the company plans to extend its 6F² architecture while developing 3D DRAM as a longer-term alternative.

Explaining the decision, DeBoer said DRAM bit density is primarily determined by capacitor pitch rather than cell architecture alone. He also pointed to fundamental scaling limitations, greater manufacturing complexity, and higher costs associated with 4F², according to the webinar transcript published by Stock Analysis.

Micron Extends Planar DRAM Roadmap Beyond 1δ

Beyond its decision to retain the 6F² architecture, Micron also outlined its planar DRAM roadmap. Its 1γ (1-gamma) node is already in high-volume manufacturing and will underpin products introduced over the next 12 months, according to MarketBeat.

The next node, 1δ (1-delta), is expected to enter volume production in the second half of 2027, targeting a bit-density improvement in the mid-20% range. According to Wccftech, it will support next-generation memory products including DDR6, LPDDR6, HBM5, and vertical HBM (vHBM).

Further along the roadmap, Micron is developing its 1ε (1-epsilon) node with wafer bonding to improve bit density and support AI applications, according to the webinar transcript published by Stock Analysis. For its subsequent 1ζ (1-zeta) and 1η (1-eta) nodes, the company is exploring High-NA EUV, new materials, and other innovations to extend planar DRAM scaling.

Notably, Micron’s roadmap places 3D DRAM between the 1ζ and 1η nodes, but development is proceeding in parallel with planar DRAM, with adoption depending on cost, manufacturing complexity, and device performance, according to the webinar transcript published by Stock Analysis.

Next-Generation DRAM Products and HBM Architecture

Building on these advances, Micron is preparing DDR6 and LPDDR6, targeting twice the bandwidth of DDR5 and a 35% improvement in power efficiency over LPDDR5, respectively, with greater efficiency gains at certain densities. The company also plans a 1TB RDIMM following its recent sampling of a 512GB DDR5 RDIMM.

For AI applications, Micron is also advancing vertical high-bandwidth memory (vHBM), which stacks memory directly on processing chips to deliver substantially higher bandwidth. According to MarketBeat, the company is developing vHBM alongside standard and custom HBM products, although thermal management remains a challenge. Its packaging efforts include hybrid bonding for tighter interconnect pitches and higher bandwidth, taller HBM stacks, and improved cooling technologies, the report notes.

Turning to NAND, Micron plans to ramp its Generation 11 (G11) technology in the second half of 2027. G11 targets twice the bit density of G9 NAND, 1.5 times the I/O speed, and lower data-transfer energy consumption. It will also adopt wafer-on-wafer bonding and feature more than 400 layers, as noted by MarketBeat.

Read more

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(Photo credit: Micron)