[News] JEDEC Unveils First Industry-Wide Silicon Photonics Reliability Standard, Setting Rules Across Four Key Areas

As Intel, TSMC, Samsung and other chipmakers accelerate their push into silicon photonics, the technology has gained its first industry-wide reliability standard. In early October, JEDEC unveiled JESD264, establishing qualification and reliability requirements for silicon photonics (SiPh) devices.

The key features of JESD264 highlighted by the association span four areas: comprehensive reliability protocols for SiPh dies and integrated chipsets; guidelines for component-level qualification, including modulators, photodiodes and waveguides; clear requirements for assembly processes and laser integration; and expectations for manufacturing process control and traceability.

As highlighted by Electronics Weekly, unlike mature CMOS technologies, silicon photonics has lacked standardized, industry-wide practices for qualification and reliability validation.

Taiwan-based semiconductor testing firm MAtek further explains that while conventional CMOS qualification largely focuses on electrical performance, materials and package durability, photonic integrated circuits (PICs) bring together optical waveguides, couplers, splitters, modulators, photodetectors and associated electronics. Electrical testing alone may therefore miss optical-specific failures, including power degradation, insertion-loss changes, wavelength drift and coupling misalignment.

According to MAtek, those reliability challenges become even more pronounced as integration scales up, with CPO, 2.5D/3D chiplets and multi-chip modules bringing optical components, electronic dies, substrates, fibers and lasers into increasingly dense packages, where thermal expansion, warpage, bonding, optical alignment and interface defects can worsen under temperature, humidity or mechanical stress. That makes reliability validation increasingly a system-level challenge.

JESD264 is intended to address that gap. According to JEDEC, JESD264 is designed to provide a common foundation for chip designers, foundries, OSATs, module makers and system developers, bringing greater consistency to silicon photonics qualification as the technology moves toward broader adoption.

Semiconductor Giants Step up Silicon Photonics Development

Major chipmakers are also stepping up efforts to commercialize silicon photonics. As noted by ZDNet, during its first-quarter earnings call, Samsung said its foundry business had secured an order from a major optical communications module provider, establishing a foothold in silicon photonics.

TSMC, meanwhile, announced in May that the world’s first 200Gbps micro-ring modulator (MRM) featuring its Compact Universal Photonic Engine (COUPE) technology will enter mass production by year-end, Economic Daily News reports. As noted by Tom’s Hardware, TSMC’s silicon photonics roadmap unfolds in three stages, scaling from a 1.6 Tbps optical engine paired with conventional pluggable optics to a 12.8 Tbps engine integrated directly within the processor package.

In terms of Intel, Tom’s Hardware explains that the chipmaker’s CPO strategy centers on its Optical Compute Interconnect (OCI) chiplet, a self-contained optical I/O subsystem integrating both electronic (EIC) and photonic (PIC) dies. Designed to be co-packaged with CPUs, GPUs and other compute chips through a PCIe interface, OCI aims to bring high-bandwidth optical connectivity directly into the package, the report suggests.

Read more

• [News] TSMC Targets 2H26 COUPE on Substrate; NVIDIA Could Eye Long-Term Substrate Deals Amid CPO Push
• [News] Silicon Photonics Race Intensifies as TSMC Targets 2026 COUPE Production, Samsung Eyes 2029 CPO Turnkey

(Photo credit: Intel)