[News] Chinese Researchers Reportedly Push GAA With DUV, Opening Potential Path to 3nm-Level Performance

China is exploring new ways to advance its chipmaking capabilities despite limited access to EUV lithography. According to Wccftech, the Chinese Academy of Sciences (CAS) has reportedly developed a new gate-all-around (GAA) transistor architecture that could provide a pathway toward 3nm-equivalent performance using DUV lithography, although major scaling and interconnect challenges remain.

The new GAA transistors reportedly achieve on-off ratios above 500,000, meaning the current flowing through a transistor when it is switched on is more than 500,000 times greater than when it is off. The result indicates strong electrical control while significantly reducing leakage current, the report notes.

Notably, CAS claims the new GAA transistors were fabricated using DUV lithography. While DUV does not normally offer sufficient resolution to print 3nm-level circuits, the report notes that techniques such as multi-patterning, which uses repeated patterning and etching steps to create finer features, and immersion DUV, which uses ultra-pure water to improve resolution, can enable 7nm-level circuits.

The reported gains are primarily at the transistor level, which falls within the front-end-of-line (FEOL) stage of chip fabrication. According to the report, the stronger electrical control of the new GAA design could allow transistors to be spaced somewhat farther apart while still delivering performance comparable to a more tightly packed FinFET design. This could ease lithography requirements at the transistor level, making such structures more feasible to fabricate using DUV.

Interconnect Challenges Could Limit the Gains

However, improvements at the transistor level do not eliminate challenges elsewhere in the manufacturing process. As the report notes, the middle-end-of-line (MEOL) forms the contacts that connect individual transistors to the wider circuit, requiring extremely precise trenches and holes to be etched and filled with metal. The back-end-of-line (BEOL), meanwhile, forms the metal wiring layers that connect components across the chip, including M0, the lowest metal interconnect layer and one of the most difficult to fabricate because of its tight dimensions and proximity to the transistors.

A semiconductor expert cited by Wccftech argues that MEOL contact formation and the M0 interconnect layer remain key scaling challenges for SMIC, and that improvements to the GAA transistor itself would not address these bottlenecks.

China Explores Other Paths Beyond Process Scaling

China is also exploring other approaches to push chip capabilities further. According to the South China Morning Post, Huawei’s recently unveiled Kirin 9050 Pro uses its LogicFolding architecture, which stacks two layers of logic vertically and connects them through vertical interconnects. Huawei says the approach increases transistor density from 155 MTr/mm² to 238 MTr/mm² by packing more logic into the same area rather than relying on further process scaling.

Read more

• [News] NVIDIA CEO Jensen Huang Reportedly Says China Could Develop Advanced Lithography Systems by 2030
• [News] Huawei Reportedly Backs China’s DUV Drive, with 12 Systems Targeted by End-2026; SMIC Testing Underway

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