[News] TSMC Touts Unmatched 5x Reticle-Size Packaging Prowess and High Yields, Ready to Step In if Rivals Fall Short

Vowing to “leave no food on the table,” TSMC is doubling down on advanced packaging despite its own CoWoS capacity constraints. According to TechNews, CEO C.C. Wei highlighted TSMC’s ability to mass-produce 5x reticle-size packaging with strong yields—a feat he says rivals have yet to match.

With 9x solutions under development and 14x on the horizon, the foundry giant is pushing the boundaries of advanced packaging. Wei also signaled that TSMC could step in if rival providers, including Intel’s EMIB, struggle to meet customer demand.

As reported by Anue in August, TSMC Vice President of Advanced Packaging Technology and Service Jun He revealed that the company’s 5.5x reticle-size CoWoS technology has already entered high-volume production, with yields exceeding 98% for multiple AI customers and reaching as high as 99% for some.

With TSMC advancing its CoWoS technology at a pace of one generation per year, the foundry giant expects to scale up to 14x reticle-size packaging by 2029, according to Anue.

A14 Could Become Bigger Than N2, TSMC Says

TSMC CEO C.C. Wei expects the company’s next-generation A14 process to become an even larger node than N2, citing stronger customer engagement, according to TechNews. The 1.4nm-class technology is slated to enter risk production in 2027, followed by high-volume manufacturing in 2028.

Meanwhile, rival Intel is accelerating its 14A roadmap. According to Wccftech, CEO Lip-Bu Tan is reportedly targeting risk production as early as 1Q27, although Intel’s official timeline remains more conservative, with internal 14A products planned for 2H27 and high-volume manufacturing in 2028.

Intel’s push into advanced nodes has also raised questions about whether major IDMs could shift more chip production in-house, potentially reducing their reliance on TSMC. Addressing such concerns, Wei stressed that the foundry treats all customers equally, whether IDMs or fabless chip designers, while factoring their internal manufacturing capacity into its own capacity planning and support commitments.

Intel’s shift toward in-house production may already be taking shape. According to a July TechPowerUp report citing KeyBanc, Intel reportedly plans to manufacture 80–90% of its upcoming Nova Lake compute tiles internally, reversing an earlier dual-source strategy under which TSMC’s N2 process was expected to handle 60–70% of production, with Intel’s 18A accounting for the rest.

Read more

• [News] TSMC Lifts 2026 Growth Forecast to 44%, Eyes Record 4Q Revenue of Up to US$54.3B, Up 14% QoQ
• [Breaking] Intel EMIB Substrate Yields Reportedly Hit 45%, Suppliers Eye 60% by 1Q27

(Photo credit: TSMC)