The 2026 OCP Global Summit took place from October 12 to 15, 2026. During the summit, key industry players—including SK hynix, Metrum AI, Solidigm, and Nallasway—unveiled pivotal memory architecture innovations. Whether leveraging HBF, shared SSD pools, or external DRAM modules, solution developers are aligning around a common strategy: expanding AI memory beyond the single HBM tier to break through the memory wall bottleneck in the AI era.

Accordingly, this report delivers an in-depth analysis of key memory hierarchy expansion strategies designed to overcome the memory wall, examining solution developers’ roadmaps across three primary initiatives: (1) SK hynix—MARS and HBF; (2) Metrum AI and Solidigm—shared SSD KV cache pool; and (3) Nallasway—new XPU module.

Key Highlights

• At the OCP Global Summit, SK hynix, Metrum AI, Solidigm, and Nallasway unveiled next-generation memory architectures. 
• The industry’s shared direction is to extend AI memory beyond the single HBM tier to break through the “memory wall” bottleneck. 
• Three main approaches: SK hynix’s MARS and HBF; Metrum AI and Solidigm’s shared SSD KV cache pool; and Nallasway’s new XPU module. 

Table of Contents

1. SK hynix－MARS and HBF
   • Figure 1: From Processor-Centric to Memory-Centric
   • Figure 2: SK hynix’s Memory-Centric AI Rack System (MARS)
   • Figure 3: Performance of MARS in Multi-Turn AI Agent Applications
   • Figure 4: Performance of MARS in Personal AI Agent Voice Interaction Applications
   • Figure 5: Performance of MARS in GNN Training Applications
   • Figure 6: Performance Comparison Across HBF, HBM, and eSSD
   • Figure 7: Schematic Diagram of the HBF Architecture
   • Figure 8: HBF Development Roadmap
2. Metrum AI and Solidigm—Shared SSD KV Cache Pool
   • Figure 9: Empirical Benchmark Data for Metrum AI’s Shared SSD KV Cache Pool
   • Figure 10: Empirical Benchmark Data for Solidigm’s D7-PS1010 and D5-P5336
   • Figure 11: Efficiency Gains of SSDs in KV Cache Compression
3. Nallasway – New XPU Module
   • Figure 12: Comparison of Nallasway’s New XPU Module and Alternative Memory Interconnect Architectures
   • Figure 13: Schematics of Credo’s OmniConnect
   • Figure 14: Schematics of Credo’s OmniConnect Weaver 1
   • Figure 15: Schematics of Connective Architecture for New XPU Module
   • Figure 16: Schematics of Lotes’ PrezLink CPC Connector
   • Figure 17: Schematics of Physical Architecture for New XPU Module
   • Figure 18: Schematics of Power Supply Architecture for New XPU Module
   • Figure 19: Schematics of CreAlien Hybrid Single/Two-Phase Liquid Cooling
   • Figure 20: Schematics of ORV3 2OU Chassis
4. TRI’s View

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