[News] Huawei Scientist: EDA Tools Pose Biggest Challenge to Tau Scaling Law

Huawei’s  Tau (τ) Scaling Law faces its greatest challenge in electronic design automation (EDA) tools, according to Huang Yu, chief scientist for semiconductor EDA at Huawei, speaking at the 2026 Bay Area Chip Expo on October 15, media reports said.

Huang outlined four layers of Tau (τ) Scaling Law.

At the device level, the focus is on optimizing transistor structures and interconnects to reduce device time constants at the source.

The second is the link layer, which he described as the company’s biggest area of innovation.

The third is the chip layer, where hardware-software co-design enables new architectures.

The fourth is the system layer, encompassing technologies such as supernodes and rack-scale interconnects that require better communication protocols and higher speeds.

“The biggest challenge for Tau (τ) Scaling Law lies in EDA tools,” Huang said, adding that process technology, engineering, and system design also present challenges.

 Tau (τ) Scaling Law Evolves from Theory to Commercial Reality

Huawei formally introduced  Tau (τ) Scaling Law on May 25, 2026, at the IEEE International Symposium on Circuits and Systems (ISCAS 2026). Proposed by He Tingbo, president of Huawei’s semiconductor business, the principle outlines a new approach to semiconductor industry development.

The theory seeks to address the limitations of Moore’s Law, which has traditionally relied on transistor scaling to improve performance as devices approach physical limits and manufacturing costs rise. Tau (τ) Scaling Law proposes “time scaling” as an alternative to geometric scaling, focusing on reducing signal propagation and processing delays across electronic systems.

Meanwhile, He published a paper titled A Time Scaling Theory for Multi-Layer Electronic Systems on ChinaXiv, the Chinese Academy of Sciences’ preprint platform, detailing the initial theoretical framework.

In July, Huawei released Version 2 of the paper, adding engineering implementation details, measured quantitative data, and product development roadmaps. It also introduced key engineering concepts, including the “gear ratio,” further developing the theory into a more complete framework.

In October, Huawei launched the Mate 90 series, with all models featuring the Kirin 9050 Pro chip based on the “LogicFolding” technology associated with Tau (τ) Scaling Law, marking the theory’s transition from concept to commercial product.

At Huawei’s Terminal Innovation Technology Briefing on October 13, the company said LogicFolding had been commercialized for the first time in the Kirin 9050 series. Rather than simply stacking multiple chips, the approach incorporates three-dimensional system-level design from the outset, distributing logic circuits in more suitable locations and co-designing multiple dies as a unified chip. This reduces signal routing lengths, increases transistor density, and improves performance and power efficiency.

(Photo credit: Huawei)