[News] AMD EPYC Venice CPUs Begin Shipping on TSMC 2nm; Verano Reportedly to Adopt N2P, with A14 Planned for 2028

AMD is expanding its server CPU offerings to meet growing demand for agentic AI, driving opportunities for advanced semiconductor manufacturing and packaging. According to Commercial Times, Taiwanese partners including TSMC, ASE, SPIL, and Powertech Technology (PTI) are expected to play key roles in supporting AMD’s next-generation server processors.

AMD has begun shipping its Venice SP7 processors, with the enterprise-focused SP8 platform expected to follow in the first half of 2027. Verano and Venice-X are scheduled to ship in the second half of 2027, Commercial Times reports.

Venice combines TSMC’s N2 process with CoWoS-L advanced packaging, while the subsequent Verano platform is set to adopt the N2P node, Commercial Times highlights. Citing supply chain sources, the report adds that AMD plans to adopt TSMC’s A14 process for its Zen 7 architecture, expected to debut in 2028. The Next Platform adds that Venice uses TSMC’s 6nm process for its I/O dies, alongside its 2nm compute chiplets.

Beyond advanced manufacturing, AMD is strengthening its packaging partnerships in Taiwan. According to Commercial Times, ASE and SPIL are participating in the development and validation of wafer-level 2.5D bridge interconnect technology, while AMD has completed validation of panel-level embedded fan-out bridge (EFB) interconnect technology with PTI.

AMD Expands EPYC Performance and AI Rack Ecosystem

Venice offers high-density configurations with up to 256 cores and 512 threads for running multiple AI agents simultaneously, alongside high-frequency models reaching 5.3GHz for faster response times and GPU support. As noted by Economic Daily News, AMD shows that the SP7 platform delivers up to twice the performance of its predecessor, Turin, and 40% better performance per watt in general-purpose workloads.

AMD is also extending its sixth-generation EPYC processors into rack-scale AI systems. In its November 10 announcement, the company introduced Helion rack configurations designed for agentic AI workloads, with some high-density systems supporting up to 73,728 threads per rack. The rack-scale expansion is also creating opportunities for Taiwanese server manufacturers. According to Economic Daily News, Foxconn, Compal, Inventec, and Wiwynn are among the partners supporting AMD’s Helion rack ecosystem, which includes more than 10 certified configurations, with initial shipments expected to begin in November.

As agentic AI drives demand for server CPUs, AMD expects the addressable data center CPU market to grow from US$26 billion in 2025 to US$220 billion by 2030, representing a compound annual growth rate of over 50%, according to Commercial Times and Economic Daily News.

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(Photo credit: AMD)