AI-driven semiconductor demand is reportedly fueling another round of price increases across the OSAT industry. According to MoneyDJ, citing industry sources, ASE, the world’s leading outsourced semiconductor assembly and test (OSAT) provider, has raised its packaging quotes by more than 20%, driven by higher raw material costs and higher long-term investment costs.

The latest price increases cover advanced packaging technologies such as Chip-on-Wafer-on-Substrate (CoWoS) and Fan-Out Chip on Substrate (FoCoS), with major U.S. customers among those affected, the report says.

ASE declined to comment on the market speculation, the report adds.

The report indicates that ASE has become a key beneficiary of the AI-driven advanced packaging boom. With TSMC’s CoWoS capacity still supply-constrained and outsourcing continuing to increase, the company is seeing stronger demand for its on-substrate (oS) packaging and chip probing (CP) services.

Meanwhile, utilization rates across the OSAT industry remain near full capacity, with both leading and smaller providers actively expanding capacity to meet rising demand, the report notes.

AI Fuels OSAT Investment and Capacity Expansion

Commenting on the pricing strategy, ASE COO Tien Wu said the increases reflect two key factors: higher raw material costs and growing capital investment requirements, according to MoneyDJ.

Those long-term investments are being fueled by AI. According to Liberty Times, Wu said AI has become the key driver behind ASE’s capacity expansion plans. As AI adoption extends beyond data centers into physical AI applications such as automotive electronics and humanoid robots, he described the trend as a long-term structural shift and said the ASE Group is “going all out” to expand capacity.

To support future demand, Wu estimates that ASE and its subsidiary SPIL have around 15 new factory projects underway this year to prepare for demand expected from 2029 to 2030 and beyond, according to Liberty Times. ASE increased capital expenditures to US$5.3 billion in 2025 and further raised its 2026 capex to US$8.5 billion, with additional increases remaining possible.

The aggressive capacity expansion reflects a broader industry trend. As noted by Economic Daily News, competition in AI has expanded beyond leading-edge processes, making backend packaging, testing, and assembly increasingly critical to chip performance, yields, and time-to-market. As a result, major OSAT providers are accelerating investments in technologies such as 2.5D/3D packaging, chiplets, HBM integration, and panel-level packaging, further positioning the sector as a key capacity bottleneck in the AI semiconductor supply chain.

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(Photo credit: ASE)

Elon Musk’s Terafab project has added an Intel veteran to its leadership team. According to Wccftech, Gary Jiang is Tesla’s first major hire for the initiative. Jiang announced the move on his LinkedIn profile, where he lists his new role as Director, Tera Fab, a position he assumed in June 2026 and is based in Austin, Texas.

As highlighted by the report, Jiang spent nearly 18 years at Intel before joining Tesla. Most recently, he served as a Factory Manager at Intel’s Arizona operations, where he helped prepare the company’s facilities for the 18A manufacturing ramp. Earlier in his career, he oversaw high-volume manufacturing for Intel’s 22nm and 14nm processes.

The report suggests that Jiang’s experience building and managing semiconductor manufacturing operations likely contributed to his recruitment for the Terafab project. It also notes that Intel, his former employer, is partnering with Tesla and SpaceX on Terafab through its 14A process.

Electrek notes that hiring an Intel 18A factory manager as Director of Terafab marks a meaningful step in building Tesla’s semiconductor manufacturing expertise. However, the report cautions that a single leadership hire cannot replace the decades of experience and institutional knowledge required to operate a leading-edge fab, and that the greater challenge will be successfully executing the project and achieving high production yields.

The appointment comes as Terafab continues to gain momentum. Reuters recently reported that Elon Musk has outlined the project’s vision at an ASML event, with the Dutch lithography leader expected to play a key role in the initiative.

The hiring also follows recent progress on Terafab’s development. As noted by Reuters, Grimes County recently approved tax incentives for the proposed semiconductor campus, paving the way for the project to move forward.

Reuters also reports that SpaceX and its partner Tesla will invest an initial US$55 billion in the project, with total investment potentially reaching US$119 billion if it is fully built out.

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(Photo credit: Intel on X)

According to TrendForce’s latest memory spot price trend report, DRAM spot prices this week have seen upward momentum in low-density DDR4 and DDR3 segments, while the broader market continues to trend sideways. In NAND Flash, suppliers are adjusting quotations to optimize inventory levels, but buyers remain reluctant to accept current pricing, with 512Gb TLC wafer spot prices continuing to decline.

DRAM Spot Price:

Upward price momentum in the DRAM spot market this week has been concentrated on low-density DDR4 and DDR3 chips, while the broader market continues to trend sideways. Although sporadic inquiries for other chips exist, overall trading volume is still rather low because quotes are holding at high levels, and buyers are reluctant to chase higher prices. The average spot price of mainstream chips (i.e., DDR4 1Gx8 3200MT/s) has risen by 0.28% from US$35.900 last week (June 24) to US$36.00 this week (June 30).

NAND Flash Spot Price:

Spots remain partially sluggish, where dynamics of demand are visibly withering and continue to hit rock bottom. The supply end has alleviated quotations to adjust inventory, though buyers are exceedingly on stocking activities as they are obviously hesitant towards accepting the existing level of cost, having reached the limit of tolerance. Overall prices are fully deprived of momentum of increment as the market lacks substantial buy orders, and remain on the weaker end. 512Gb TLC wafer spots dropped by 1.03% this week (June 29), arriving at US$19.862.

Price increases are spreading across the passive component industry. According to Economic Daily News, sources say YAGEO has notified customers of price increases across its entire capacitor solutions portfolio, effective July 1. The hike covers MLCCs, aluminum electrolytic capacitors, tantalum capacitors, polymer aluminum capacitors, film capacitors, and supercapacitors, marking the company’s broadest price increase in recent years.

Institutional investors cited by the report say capacitors account for about half of YAGEO’s revenue and expect the latest price hike to boost both revenue and profitability while also benefiting other Taiwanese passive component suppliers.

Commercial Times also notes that YAGEO is raising MLCC prices for direct customers for the first time, extending the increase beyond distributors to both contract and spot pricing. Given that direct customers account for more than half of the company’s revenue, the report says the move is expected to provide a meaningful boost to sales.

As for the scale of the increases, Shanghai Securities News, citing industry sources, reports that YAGEO has raised its official prices for capacitor products by around 50%, with even steeper increases in the spot market. The report also notes that spot-market prices have continued to climb since May, with prices for high-end capacitor products rising by as much as nearly tenfold within a month. Delivery delays have also become increasingly common, affecting not only YAGEO but major MLCC brands across the industry.

Cost Pressures Drive Broad Price Hikes

As noted by Economic Daily News, the price hike reflects rising manufacturing costs driven by geopolitical risks, elevated energy prices, and higher raw material costs. The report says YAGEO had previously absorbed these pressures through process optimization and supply chain integration, but ongoing tensions in the Middle East and volatile freight rates have prompted the company to adjust prices.

The increase is also broad in scope. The report adds that it spans YAGEO’s entire capacitor portfolio, covering products used in AI servers, consumer electronics, automotive, industrial, renewable energy, aerospace, power, and energy storage applications.

AI Reshapes the MLCC Market

Meanwhile, institutional investors cited by Economic Daily News note that continued growth in AI servers, high-performance computing (HPC), and electric vehicles is driving both the volume and specifications of high-end passive components. The report says demand for higher-capacitance, higher-voltage, and higher-reliability products is increasing overall capacity consumption.

Commercial Times also notes that as thermal design power (TDP) and power requirements for AI server racks continue to rise, particularly with the fourth-quarter ramp of NVIDIA’s Vera Rubin platform, passive components are playing an increasingly critical role in 800V HVDC power architectures. As a result, passive components have climbed from near the bottom of the bill of materials (BOM) cost ranking to second only to GPUs and memory.

Against this backdrop, Commercial Times further notes that YAGEO is expected to be the largest beneficiary of MLCC order transfers as Murata and Samsung Electro-Mechanics shift capacity toward higher-value AI MLCCs. High-capacitance MLCCs require 500–1,300 layers, compared with 50–100 layers for low-capacitance products, making them more capacity-intensive and reducing yields. With Japanese and South Korean manufacturers already operating at full utilization, the report says supply of conventional MLCCs is becoming increasingly constrained.

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(Photo credit: YAGEO)

As interest in Intel’s foundry services continues to grow among a broader range of tech giants like Apple and NVIDIA, the chipmaker is accelerating its U.S. manufacturing buildout. According to Wccftech, Intel has officially broken ground on the latest expansion of its Santa Clara, California campus, with CEO Lip-Bu Tan and other senior executives attending the ceremony.

The expansion project was originally scheduled to begin in mid-2026, with the latest groundbreaking indicating that the timeline remains on track, the report adds.

Separately, policy timing could add further pressure to the buildout schedule, with a previous Tom’s Hardware report noting that semiconductor and advanced manufacturing projects must break ground by December 31, 2026, to qualify for the 35% Investment Tax Credit, and that projects initiated in 2027 or later will no longer be eligible for the incentive.

According to the San Francisco Business Times, Intel’s Santa Clara Bowers Campus development spans a 107,000-square-foot site and will include two three-story buildings dedicated to manufacturing, fabrication, and central utility operations. Wccftech adds that the site will support the production of EUV photomasks (reticles) critical to next-generation process nodes, including 18A-P and 14A.

Intel’s U.S. Expansion Roadmap in Focus

As Intel ramps up its 18A and 14A efforts, Fab 52 at the company’s Ocotillo campus in Chandler is set to serve as a key manufacturing backbone, according to Tom’s Hardware. The facility entered full-scale production in October 2025 as Intel’s first high-volume 18A site, initially producing Panther Lake compute tiles before expanding to Clearwater Forest later this year.

Notably, the report, citing CNBC, also highlights that Fab 52 is designed to support more than 10,000 Intel 18A wafer starts per week. At full ramp, this reportedly translates to roughly 40,000 wafer starts per month—exceeding the combined output of TSMC’s Fab 21 Phase 1 and Phase 2 in Arizona.

The next major Arizona expansion phase would be Fab 62, which is expected to enter production around 2028, according to Tom’s Hardware. While Intel has not disclosed its process node, Fab 62 is expected to provide flexibility to support either 14A production if Ohio falls behind schedule, or additional 18A capacity should demand outpace expectations, the report suggests.

Against this backdrop, Ohio, meanwhile, remains the most delayed project in Intel’s pipeline. After breaking ground in 2022 on a US$28 billion investment, the company has pushed Phase 1 completion to 2030 with operations in 2030–2031, followed by Phase 2 production in 2032.

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(Photo credit: Intel)

On June 24, 2026, Hangzhou Garen Semiconductor announced a major commercialization milestone: the company has successfully established the world’s first mass-production line compatible with both 6-inch and 8-inch homoepitaxial gallium oxide wafers. The company has already delivered 6-inch (100)-oriented homoepitaxial gallium oxide wafers to leading chipmakers, marking its entry into stable volume production and supply.

The global gallium oxide industry has long been constrained by small wafer sizes, limited production capacity, and poor uniformity. Most commercially available products have been restricted to 2-inch to 4-inch wafers, making large-scale manufacturing of advanced power devices difficult.

By establishing a complete mass-production process, Garen claims to have overcome key commercialization barriers and become the world’s first—and currently only—supplier capable of commercially delivering 6-inch homoepitaxial gallium oxide wafers.

The production line combines Garen’s proprietary cast-growth single-crystal technology with an optimized MOCVD epitaxy process. The in-house crystal growth method enables the production of ultra-thick gallium oxide crystals, while an ultra-thin substrate process increases substrate output by three to four times compared with conventional approaches.

The technology also significantly reduces iridium consumption, lowering substrate costs by more than 80% per wafer and helping cut material costs for downstream device manufacturers.

Product qualification data released by the company show that its 6-inch homoepitaxial gallium oxide wafers feature epitaxial layers exceeding 10μm in thickness, with thickness variation below 1%. The high level of uniformity is expected to support improved yields for high-performance devices designed for high-voltage, high-frequency, and high-temperature applications.

On the manufacturing side, Garen has established a fully integrated production chain covering single-crystal growth, substrate processing, and homoepitaxy. The 6-/8-inch compatible production line has reportedly achieved stable and controllable batch quality. In addition to long-term supply agreements with major domestic chipmakers, the company said that several overseas enterprises and research institutions have also placed orders, accelerating commercial adoption.

Gallium oxide, an ultra-wide-bandgap semiconductor material, offers high breakdown field strength, low conduction losses, and strong high-temperature performance. It is considered a promising material for applications including high-voltage power grids, electric vehicles, photovoltaic energy storage systems, and advanced RF communications.

The transition to larger wafer sizes is expected to significantly improve manufacturing efficiency, with an 8-inch wafer capable of producing roughly four times as many chips as a 4-inch wafer, enhancing the economics of large-scale production.

(Photo credit: FREEPIK)

The trend toward long-term supply agreements is expanding beyond memory, with tightening MLCC supply prompting major tech companies to secure component availability. According to ZDNet, Samsung Electro-Mechanics has signed a one-year supply contract with a major customer for multilayer ceramic capacitors (MLCCs) used in AI servers.

As noted by Global Economic News, Samsung Electro-Mechanics announced on June 30 a KRW 450 billion (USD 330 million) supply agreement with a global big tech customer for AI server MLCCs. The contract will run for one year, from January 1 through December 31, 2027.

ZDNet highlights that such long-term agreements are rare in the MLCC industry, where short-term orders are the norm, signaling structurally stronger demand for high-performance MLCCs. While Samsung Electro-Mechanics did not disclose the customer’s identity, industry sources believe the agreement is with one of North America’s leading cloud service providers (CSPs), the report adds.

Following the agreement, Samsung Electro-Mechanics is also in talks with its global customer and other major technology companies to expand supply beyond 2027, ZDNet reports.

Samsung Electro-Mechanics is a leading supplier in the high-end MLCC market. According to Global Economic News, Samsung Electro-Mechanics currently holds 25% of the global MLCC market. In the technologically demanding AI server MLCC segment, however, the company has secured more than a 40% market share.

MLCC Demand Accelerates With AI Servers

The growing adoption of AI servers is further boosting demand for high-performance MLCCs. According to ZDNet, AI servers typically require more than 10 times as many MLCCs as conventional servers. A single GPU generally contains over 20,000 MLCCs, while a server rack can use as many as 600,000, the report notes.

According to TrendForce, the AI arms race among global CSPs is accelerating the adoption of in-house ASIC accelerators, which increasingly rely on small-form-factor, high-capacitance, high-temperature-resistant MLCCs. TrendForce expects multiple demand drivers to converge between late 3Q and early 4Q, potentially turning a latent supply risk into a tangible shortage.

Yonhap News notes that as the MLCC market becomes increasingly supplier-driven, the pricing power of major manufacturers—including Samsung Electro-Mechanics, Japan’s Murata, TDK, and Taiyo Yuden—is strengthening. The report adds that prices for some MLCC products have already increased, while long-term supply agreements (LTAs) are gaining traction.

Long-Term Silicon Capacitor Supply Agreements

The rapid growth of AI semiconductors is also lifting demand for related components, making long-term supply agreements an increasingly common way to secure stable supply. As reported by ZDNet, Samsung Electro-Mechanics also signed a KRW 1.5 trillion long-term silicon capacitor supply agreement with a major global company on May 20. The two-year contract runs from January 1, 2027, through December 31, 2028.

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(Photo credit: Samsung Electro-Mechanics)

Rising raw material costs are driving price increases among upstream electronics and semiconductor materials suppliers. According to TechNews, glass fiber cloth supplier FULLTECH and epitaxial wafer manufacturer VPEC have both issued price adjustment notices to customers, signaling mounting cost pressures across the electronics industry in the second half of 2026.

FULLTECH, a key upstream supplier of PCB materials, officially notified customers on June 26 of upcoming price increases. The company cited continued increases in glass fiber yarn costs, higher energy prices, and fluctuating transportation expenses, all of which have significantly raised production costs.

The notice states that the price adjustments cover FULLTECH’s entire portfolio of E-glass and FLD2 glass fiber cloth products. Prices for E-glass glass fiber cloth will increase by 30%, while FLD2 glass fiber cloth will rise by 15%. The new pricing will take effect for new orders placed on or after July 1, 2026.

As noted by Commercial Times, Japan’s leading glass fiber manufacturer, Nittobo, raised prices for its electronic-grade glass fiber products by 20% in 2025 and has further increased T-Glass prices by 30% this year. As low-dielectric materials such as T-Glass and NER Glass become increasingly important for AI servers, high-speed switches, and next-generation 3.2T transmission platforms, demand for high-end glass fiber cloth continues to rise.

VPEC Raises Epi Wafer Prices

Meanwhile, gallium arsenide (GaAs) epitaxial wafer manufacturer VPEC issued a price adjustment notice to its business partners on June 29, citing the continued rise in global raw material costs over the past year.

The company said it has made every effort to absorb the additional costs through internal optimization. However, after a careful internal review, VPEC decided to implement moderate price increases for its epitaxial (epi) wafers to address mounting operating pressures while ensuring the continued delivery of high-quality products. The exact adjustment will vary by product.

As major upstream suppliers continue to implement price increases, the resulting cost pressures are expected to gradually pass through to downstream manufacturers and brand owners during the third quarter, TechNews notes.

According to TechNews, the price hikes announced by FULLTECH and VPEC represent only the “tip of the iceberg” of inflation in electronic raw materials. Spanning everything from glass fiber cloth to epitaxial wafers, the announcements point to broad-based, systemic cost pressures across the electronics supply chain. The report adds that whether this wave of raw material inflation triggers broader industry-wide price increases will be closely watched by the market.

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(Photo credit: Taiwan Glass)

As Intel and TSMC both target 1.4nm mass production around 2028-29, Samsung—after reportedly delaying its own roadmap—is now re-entering the race. According to The Bell, the company has resumed efforts to commercialize its 1.4nm (SF1.4) foundry process, with mass production now slated for 2029, placing it slightly behind its leading rivals.

Samsung is also understood to have recently requested early development of process equipment from domestic and overseas partners. As noted by the report, it has recently shared its 1.4nm process roadmap with major semiconductor equipment makers, including Applied Materials and Lam Research.

Notably, the report, citing industry sources, points out that Samsung Electronics has already installed ASML’s next-generation High-NA extreme ultraviolet (EUV) lithography equipment at its NRD-K facility. The High-NA EUV tools are understood to be applied to select layers starting from the 1.4nm process, the report explains.

Why Samsung Delayed 1.4nm Plans

The Bell adds that the original 2027 target has been pushed back to 2029, as Samsung redirects focus toward strengthening its 2nm (SF2) and derivative SF2P processes, signaling a shift toward yield stabilization and process optimization over aggressive node advancement.

This strategic pivot is also reflected at the product level. A previous Global Economic News report suggested that Samsung has shifted the manufacturing process for its next-generation flagship smartphone processor, the Exynos 2800, from the originally planned 1.4nm node to an advanced version of its 2nm process.

A Closer Look at 1.4nm Plans for Intel, TSMC

Samsung Electronics’ renewed push into its 1.4nm process is drawing attention over whether it can narrow the technology gap with rivals such as TSMC and Intel. According to Economic Daily News, TSMC is targeting 1.4nm pilot production as early as 3Q27, with mass production planned for 2H28.

However, Tom’s Hardware notes that TSMC is expected to skip ASML’s High-NA EUV tools through 2029, meaning its 1.4nm node would proceed without the advanced system being adopted by Intel and Samsung.

For Intel, Reuters reports that its 18A-P process has already entered pilot production, with the company reportedly targeting 14A risk production in 2028, followed by high-volume manufacturing in 2029.

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(Photo credit: Samsung)

China’s tech giant ByteDance is accelerating its push into custom AI chips. According to South China Morning Post, sources say the company aims to finalize the design of its next-generation in-house CPU by early 2027, with mass production and broader deployment targeted for the second half of the year.

An earlier version of the proprietary CPU has reportedly been in internal use since late 2025, with strong demand potentially bringing forward the tape-out of the new chip.

The reported development underscores ByteDance’s broader push into in-house silicon to support rising AI computing demand from products such as Doubao and Seedance. While the company has rapidly expanded its chip design efforts, it has yet to publicly disclose its progress, the report adds.

The initiative also comes as the role of high-performance CPUs is being re-evaluated in the era of agentic AI, with workloads evolving from pure matrix computation to more complex task orchestration, the report notes.

As ByteDance expands its in-house chip capabilities, Investing.com states that Arm, Intel, and AMD are among the suppliers the company could increasingly bypass.

Reuters also notes that ByteDance currently relies on CPUs from Intel and AMD, both of which have significantly raised prices in recent months, with quarter-over-quarter increases of 10% to as much as 35%.

Qualcomm Partnership and Supply Constraints

ByteDance is reportedly in discussions with U.S. chipmaker Qualcomm, which has been expanding its presence in AI data centers. As South China Morning Post notes, partnering with Qualcomm—which relies on foundries such as TSMC for manufacturing—could help ByteDance navigate an advanced chip supply chain constrained by bottlenecks spanning wafer fabrication to advanced packaging.

Last week, Qualcomm announced that Meta will adopt its Dragonfly C1000 data center CPU and disclosed that it is also developing custom silicon for two other unnamed hyperscalers, South China Morning Post adds. The company expects its data center chip business to generate US$5 billion in revenue in fiscal 2027, including US$1 billion from custom chip customers.

ByteDance Diversifies AI Chip Supply

Beyond its in-house CPU efforts, ByteDance and other leading Chinese cloud providers have increasingly turned to domestic AI chip suppliers amid the global supply crunch, including Biren Technology, MetaX, Iluvatar CoreX, Moore Threads, and Enflame Technology, as noted by South China Morning Post.

Reuters also reports, citing sources, that ByteDance is in discussions with Shanghai-based Iluvatar CoreX, one of China’s leading GPU startups, to acquire AI chips for inference workloads. Iluvatar CoreX is expected to supply at least 50,000 chips to ByteDance this year, while ByteDance is also evaluating a similar partnership with Baidu.

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(Photo credit: ByteDance)

The global semiconductor industry is set to enter a new Warring States era, as Samsung Electronics and SK hynix unveiled a sweeping investment push in South Korea. According to The Elec, the two memory giants will jointly deploy 800 trillion won to build four new fabs in the country’s southwest, alongside another 81 trillion won dedicated to a semiconductor packaging hub in the Chungcheong region.

Notably, the ripple effects are expected to extend beyond memory. As reported by Economic Daily News, the aggressive capacity expansion could ease the current severe supply shortage, while simultaneously sharpening competition with TSMC and Intel over critical semiconductor manufacturing equipment.

Rising Samsung–SK hynix Capex Tightens Chip Tool Supply

The Elec reports that the South Korean government plans to double domestic DRAM production capacity within five years. Against this backdrop, Samsung Electronics will proceed with simultaneous construction of its P5 and P6 fabs in Pyeongtaek, the report notes.

Meanwhile, SK hynix’s Yongin project timeline is also being significantly accelerated. According to Chosun Biz, the completion schedule has been advanced by 12 years from the original plan, with the fourth fab now targeted for 2033 instead of 2045.

Thus, semiconductor equipment suppliers cited by the Economic Daily News said Samsung and SK hynix’s aggressive capex will tighten competition for key advanced manufacturing tools—including EUV, etching, photomask, CMP, and deposition equipment—as they ramp capacity alongside TSMC and Intel. The resulting equipment crunch could disrupt TSMC’s and Intel’s pace of scaling sub-2nm production, the report notes.

While Samsung Electronics may benefit from bundling HBM and NAND supply with foundry services to attract AI chip demand, industry sources cited by Economic Daily News do not expect the latest investment cycle to materially shift the foundry landscape, as the company’s spending remains concentrated in memory, packaging, and infrastructure, leaving leading-edge logic production anchored by TSMC and CoWoS-based capacity.

Taiwan Memory Players Shift Toward Process Upgrades, Niche Applications

On the other hand, a separate Economic Daily News report notes that Samsung and SK hynix’s aggressive expansion move also puts Taiwan’s memory makers on high alert.

As noted by the report, Taiwan’s major memory players—including Nanya Technology, Winbond, PSMC, and Macronix—are also raising capital spending, but are focusing on process upgrades and niche applications, adopting a defensive strategy rather than competing head-on with Korean rivals on scale.

For instance, the report notes that Nanya Tech has budgeted more than NT$52 billion in capital spending this year to support product upgrades and meet supply chain demand.

According to the report, the company is expected to complete validation of its more advanced 1C (third-generation 10nm-class) 16Gb DDR5 in the second half of the year, while its 1D (fourth-generation 10nm-class) 16Gb DDR5 has already entered pilot production in the second quarter. In parallel, Nanya is reportedly working with customers on customized HBM solutions.

Read more

• [News] Samsung, SK hynix, Micron Face U.S. Class-Action Lawsuit Over Alleged DRAM Supply Manipulation
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(Photo credit: Samsung)

On June 22, a 12-inch transparent-substrate wafer facility dedicated to AR micro-nano optical products in Shanghai’s Lingang area has officially commenced operations, emerging as China’s first large-scale manufacturing base for 12-inch AR micro-nano optical wafers, according to an announcement released by China Construction Third Engineering Bureau.

With a total investment of approximately CNY 3.28 billion (USD 457 million), the project spans a gross floor area of 261,000 square meters, located in Shanghai Lingang’s Blue Bay Industrial Zone. As a key component of both Shanghai’s major municipal projects and the Lingang Oriental Chip Harbor industrial cluster, this facility is operated by Goertek OmniLight Optical Technology Co., Ltd., formerly known as Sunny OmniLight NanoOptics Technology Co., Ltd., a company previously affiliated with Sunny Optical.

In 2025, Goertek’s subsidiary Goertek Optics acquired a 100% stake in Sunny OmniLight through a capital increase of approximately CNY 530 million, integrating the company into its precision optics portfolio. The business subsequently received additional shareholder funding to further strengthen its capital base.

Construction progressed rapidly following the project’s signing in February 2023. The first production building was topped out in September 2024, the first core lithography system was moved in during July 2025, and commercial production officially began in June 2026, completing the development cycle in roughly three years and four months.

Technologically, the facility covers a range of advanced processes, including diffractive waveguide design, precision silicon carbide machining, and nanoimprint lithography. Its product portfolio focuses on high-end optical components such as AR waveguide lenses, electrochromic lenses, and microlens arrays, bringing semiconductor-grade manufacturing precision to AR optical device production.

In its 2025 annual report, Goertek stated that it would closely follow the development of large AI models and intelligent agents while expanding its presence in edge AI hardware. Key growth areas include AI smart glasses, mixed reality (MR), augmented reality (AR), and automotive electronics.

The company has continued to strengthen its position in AI smart glasses and AR optics throughout 2026 through a series of investments and strategic partnerships aimed at enhancing vertical integration.

On the manufacturing side, construction of Phase II of Goertek’s VR assembly production base began in January 2026. The project carries a planned investment of CNY 1.6 billion and is intended to expand production capacity for VR headsets and AI-powered smart glasses.

Also in January, Goertek Optics signed a joint-venture agreement with Conant Optical to jointly develop products for the AI, AR, VR, and MR eyewear markets. The collaboration covers customized prescription lenses for smart glasses, optical waveguide eyepieces for both corrective and non-corrective applications, as well as the development, manufacturing, and sales of optoelectronic components supporting electrochromic and eye-tracking functionalities.

For better development, Goertek further announced a capital injection into its subsidiary Goertek Optics alongside Sunny OmniLight in early June. The investment is intended to accelerate development in emerging optical fields, including micro-nano optical components, XR optical lenses and modules, projection optics, and automotive optical systems.

(Photo credit: Goertek)

China’s Henan provincial government website revealed that Zhengzhou High-tech Zone signed an investment agreement with Sino Powder (Henan) on June 26, establishing the company’s ultra wide bandgap semiconductor material production base.

The project is described as China’s first integrated ultra wide bandgap semiconductor industrial chain, filling a key gap in Henan’s superhard materials ecosystem by extending into high-end semiconductor substrates. Home to one of the world’s largest synthetic diamond industrial clusters, Henan aims to leverage the project to accelerate the transition of its traditional diamond industry toward advanced semiconductor materials.

Ultra wide bandgap semiconductors are based on ultra wide bandgap materials such as diamond and gallium oxide, which offer exceptional physical properties including a wide bandgap, high breakdown electric field, and superior thermal conductivity. Often referred to as the “ultimate semiconductor materials,” they are expected to support applications ranging from AI chip thermal management and 5G/6G communications to electric vehicle power electronics and advanced biomedical equipment.

With a total investment of CNY 1.5 billion (approximately USD 210 million), the project will build a complete industrial chain spanning equipment manufacturing, single-crystal growth, epitaxy processing, and packaging substrates, leveraging the company’s proprietary LPPHT micro/nanodiamond production technology. The facility will be equipped with 500 MPCVD systems for mass production of 2-inch to 4-inch single-crystal diamond wafers, alongside 50 production lines for spherical diamond powder.

Under the construction roadmap, the first 200 MPCVD systems are scheduled to enter operation by the end of 2026. Once fully ramped, the project is expected to generate annual output value of approximately CNY 3 billion within three years.

Backed by Central South University, Sino Powder is among the few Chinese companies capable of providing a fully localized supply chain for diamond semiconductor materials. Earlier this March, the company established its ultra wide bandgap semiconductor materials R&D center in Zhengzhou High-tech Zone. The newly signed production base marks the next step from laboratory research to industrial-scale manufacturing.

According to the project leader, the facility will focus on the commercialization of micro- and nanodiamond semiconductor materials while addressing the key challenge of large-scale production of high-end diamond substrates.

(Photo credit: FREEPIK)

The world’s three largest memory chipmakers—Samsung, SK hynix, and Micron—are facing a U.S. class-action lawsuit. According to IT Chosun, 17 U.S. consumers allege the three companies deliberately reduced the supply of commodity DRAM under the pretext of expanding HBM production for AI, systematically restricting supply since 2022 and driving prices up by about 700% over the past four years.

As Wccftech notes, the case, No. 3:26-cv-06345, has been classified as an antitrust lawsuit and assigned to Judge Noel Wise of the U.S. District Court for the Northern District of California.

The plaintiffs allege that the companies used inventory management as a pretext for production cuts while deliberately restricting supply to drive up prices. They are seeking a court order to halt the companies’ alleged coordinated supply restrictions and award treble damages, IT Chosun reports.

One of the central allegations is that the shift toward HBM production was part of the companies’ alleged coordinated effort to restrict commodity DRAM supply, IT Chosun notes. The complaint also contends that the three companies account for more than 90% of global DRAM sales, creating a market structure that leaves U.S. consumers heavily dependent on them.

Echoes of 2005 Price-Fixing Face New Reality of AI Shortages

To support their claims, the plaintiffs cited the U.S. Department of Justice’s DRAM price-fixing case from the early 2000s. The Biz notes that Samsung Electronics and Hynix Semiconductor (now SK hynix) pleaded guilty in 2005 and were fined US$300 million and US$185 million, respectively, for colluding on DRAM prices between 1998 and 2002, while Micron avoided penalties by cooperating with the investigation. The plaintiffs argue that the recent rise in DRAM prices reflects a repeat of that earlier case.

Still, Wccftech notes that the current situation differs from the 2005 case, arguing that today’s supply shortages are driven by surging AI demand. The report adds that the three companies have said they are expanding capacity through new fabs and production lines to increase supply.

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• [News] Lenovo Reportedly Sees Higher Memory Prices Becoming the New Normal Into 2030
• Consumer DRAM Shortages Extend to DDR2 Products with Contract Prices Expected to Continue Rising in 3Q26

(Photo credit: Samsung)

Recent geopolitical tensions have created another potential bottleneck for Korea’s semiconductor supply chain. The supply of high-purity carbon dioxide (CO₂) used in advanced semiconductor manufacturing has reportedly tightened. According to The Elec, industry sources say total inventory across the supply chain has recently fallen below one month’s supply. Under normal conditions, semiconductor manufacturers and gas suppliers each maintain about two weeks of inventory, equivalent to roughly one month’s supply in total.

Samsung Electronics is estimated to consume approximately 1,800–2,000 metric tons of high-purity CO₂ each month, while SK hynix uses roughly 600–700 metric tons, the report says.

The report notes that production at Samsung Electronics and SK hynix has not yet been affected. However, shrinking inventory buffers have prompted both companies to step up procurement efforts, although additional supply remains difficult to secure even at higher prices.

Still, according to Mydrivers, sources say that if supply tightness persists, Samsung and SK hynix’s advanced DRAM and NAND production will face pressure, making price increases inevitable.

Why High-Purity CO₂ Matters for Chip Manufacturing

High-purity CO₂ plays a key role in supercritical semiconductor cleaning processes. The Elec notes that when CO₂ exceeds its critical temperature and pressure, it enters a supercritical state that combines the properties of liquids and gases. This enables it to effectively dissolve wafer residues while penetrating deep into fine semiconductor patterns to remove contaminants, making the technology well suited for advanced semiconductor manufacturing.

The availability of high-purity CO₂ is closely tied to the supply of its upstream feedstock. As The Elec notes, CO₂ feedstock is recovered as a byproduct of oil refining, petrochemical production, and hydrogen manufacturing. Instability in crude oil supplies caused by tensions in the Middle East, coupled with lower operating rates at South Korea’s petrochemical plants, has significantly reduced the availability of CO₂ feedstock.

The report adds that liquefied CO₂ prices have risen by roughly 20% since the beginning of the year, with industry sources expecting supply tightness to persist through the end of 2026. South Korea’s major suppliers of high-purity CO₂ include Taekyung Chemical, Sundo Chemical, Dongkwang Chemical, and SK Airplus, with Taekyung Chemical recognized as the country’s leading supplier.

An industry expert cited by The Elec said geopolitical risks stemming from the Middle East are once again disrupting semiconductor material supplies, following earlier disruptions involving helium, anhydrous hydrogen fluoride, and propylene glycol monomethyl ether acetate (PGMEA).

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(Photo credit: FREEPIK)

All eyes are on TSMC ahead of its July 16 Q2 earnings, with investors watching whether the AI boom can drive another earnings beat. Commercial Times, citing analysts, says AI demand is expected to push both revenue and gross margin above guidance, with gross margin potentially nearing 70%.

The upbeat outlook is underpinned by sustained high utilization of 3nm and 5nm capacity, alongside a richer mix of AI GPU-driven advanced-node wafers and advanced packaging, the report adds. Analysts believe these tailwinds could push TSMC’s second-quarter gross margin beyond the upper end of its 67.5% guidance, bringing the 70% milestone within reach.

It is also worth noting that demand momentum is extending into next-generation nodes, with strong interest building for TSMC’s 2nm-class process in the second half. The company’s N2P variant, featuring an enhanced nanosheet architecture, is expected to enter mass production in 2026 H2, underscoring continued strength in advanced-node adoption, according to a separate Commercial Times report.

As reported by Wccftech, TSMC’s N2 is expected to power the upcoming A20 and A20 Pro chips, while the A20 Pro is also reported to adopt the new WMCM (Wafer-Level Multi-Chip Module) packaging, marking a shift away from the PoP (Package-on-Package) architecture used in the A19 Pro. On the other hand, both Qualcomm and MediaTek are expected to build their next-generation flagship mobile processors on N2P, Commercial Times adds.

3Q Revenue Poised for Fresh High

Meanwhile, with combined April-May revenue already reaching NT$827.7 billion, analysts cited by the report estimate TSMC’s June revenue could approach NT$440 billion, putting second-quarter revenue on track to exceed the upper end of the company’s guidance. According to TSMC, it guided second-quarter revenue to between US$39 billion and US$40.2 billion, based on an exchange rate of NT$31.7 to the U.S. dollar.

Notably, the report suggests that TSMC’s strong momentum is expected to carry into the third quarter, with U.S.-dollar revenue projected to grow more than 10% sequentially, pointing to yet another record-high quarter.

The growth outlook, according to Commercial Times, is underpinned by strong demand from NVIDIA’s next-generation AI GPUs, expanding AI ASIC deployments from AMD and cloud service providers (CSPs), alongside seasonal smartphone inventory builds. Against this backdrop, analysts reportedly see full-year growth potentially exceeding TSMC’s prior guidance of more than 30%.

The market is also closely watching TSMC’s advanced packaging expansion. Supply chain sources cited by Commercial Times indicate construction at the company’s Chiayi AP7 site has progressed from Phase 1 and Phase 2 toward Phase 3. Meanwhile, the report notes that the foundation work for the AP7 Phase 3 facility began in the second quarter, with the necessary construction permits recently secured.

According to Commercial Times, the site is positioned as a key hub for the company’s 3DFabric roadmap, including CoWoS, WMCM and SoIC, as overall CoWoS capacity is projected to rise from about 140,000 wafers per month this year to roughly 170,000 by 2027 as AP7 and AP8 ramp.

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• [News] Marvell Says It Is in Talks with TSMC on A14 for Next-Gen AI Connectivity Chips, Joining Early-Adopter Ranks
• [News] TSMC Reportedly Runs Dual-Track Evaluation on CoPoS Pilot Line, Sparking Global, Local Vendor Competition

(Photo credit: TSMC)

2026 is widely regarded as the first year of physical AI and agentic AI. This wave of AI adoption is sweeping across the globe, while simultaneously fueling anxiety for both individuals and enterprises. NVIDIA CEO Jensen Huang, often referred to as the “Godfather of AI,” once put it this way: “AI is unlikely to replace you, but someone who is better at using AI than you might.”

This statement captures the essence of the new AI era — whether for individuals or businesses, embracing AI is no longer optional if they want to avoid falling behind.

AI Doesn’t Have to Be All at Once — Progress Can Be Incremental

Driven by anxiety, many companies fall into the trap of believing that keeping up with AI requires massive investments in top-tier computing infrastructure from day one. Yet the pressure of such budgets often leaves them stuck in hesitation. In reality, both individuals and enterprises should choose AI tools and development strategies based on factors such as task requirements, application scenarios, and organizational adaptability.

True AI transformation requires breaking down ambitious visions into executable stages. This iterative deployment model not only helps distribute risks effectively, but also allows teams to accumulate data assets and technical confidence through real-world implementation.

More importantly, AI deployment is never a one-time build, but a gradually evolving journey—starting from the edge and progressively moving toward the core.

A Multi-Layered AI Ecosystem: Tailored Strategies from Cloud Backbone to Factory Floor

Looking across today’s global AI transformation landscape, the NVIDIA ecosystem has evolved into a diverse and complementary network of solutions designed to meet different scales and application scenarios.

On one end are the “backbone-level” solutions built by international IT giants such as Dell Technologies, Hewlett Packard Enterprise, and Lenovo, which deeply integrate powerful computing architectures into enterprise hybrid clouds and centralized data centers.

On the other end are hands-on specialists such as Advantech, companies deeply rooted in regional and vertical industries. These experts focus on factory production lines, hospital operating rooms, and logistics warehouses, striving to bridge the “last mile” of the physical edge. Their goal is to deliver highly adaptive AI solutions for frontline industries that require real-time decision-making in harsh physical environments.

No matter which direction they take, major vendors are all advancing in their respective areas of strength, collectively assembling a complete AI transformation puzzle for the market.

For most enterprises, however, the most practical path is not a leap to a fully integrated solution, but a step-by-step progression along a three-stage deployment journey that extends from the edge toward the core.

1. AI validation starting from edge nodes

Enterprises can begin by deploying lightweight edge computing modules at a single production line or key monitoring node. This step is essentially about establishing “perception capabilities” at the edge, enabling equipment to perform anomaly detection or basic decision-making. With relatively low cost and fast implementation, this stage serves as the starting point for validating AI value.

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2. AI expansion from single-point scenarios to systematic deployment

Once single-point validation is successful, AI applications begin expanding from individual nodes to multiple sites. Through industrial-grade edge AI systems, enterprises can integrate multi-point data for localized processing, enabling AI to evolve from a “tool” into a “domain capability” and deliver broader, organization-wide efficiency gains.

• Recommended reading: From Single-Task to Multi-Functional: Advantech Empowers ADATA in Developing Multi-Robot Collaborative AI AMRs

3. From data feedback loops to the core decision-making hub

As edge and field applications gradually mature, large volumes of data flow back to enterprise core systems and high-performance computing platforms for analysis and model optimization. At this stage, AI is no longer merely a frontline tool, but begins to drive enterprise decision-making in reverse, enabling the core to develop stronger predictive and strategic capabilities.

• Recommended reading: When AI Is No Longer Just a Model: Advantech and Spingence Build a Practical “Closed-Loop Path” for AI Deployment

In this AI transformation race, edge-focused specialists such as Advantech precisely embody the essence of the “Applications” layer in Jensen Huang’s “five-layer cake” theory. While NVIDIA continues pushing the limits of chips and systems at the foundational layer, industrial computing experts operating at the application layer essentially serve as “technology translators.”

Their key value lies in transforming rigid AI models and opaque computing systems into industrial-grade solutions capable of withstanding high temperatures, vibration, and dust interference, while remaining compatible with legacy machine communication protocols.As a result, frontline enterprises no longer need to spend years training highly specialized hardware compatibility experts before achieving practical AI deployment. Instead, they gain ready-to-use operational capabilities right out of the box.

Many Roads Lead to Rome — The Key Is Finding the Right Deployment Strategy

AI is reshaping the industrial landscape at an irreversible pace, and an enterprise’s position is never a static choice, but an ongoing process of dynamic evolution. The real key lies in whether organizations can clearly assess their own conditions and identify the right entry point within the broader ecosystem, then progressively advance along a path that moves from the edge toward the core, building their own AI growth trajectory.

(Photo credit: Freepik)

As AI data centers continue to scale, power consumption and bandwidth bottlenecks in chip-to-chip interconnects are becoming increasingly difficult to address. Against this backdrop, Micro LED-based co-packaged optics (CPO) is emerging as a promising alternative. By replacing traditional high-speed serial architectures with a “wide-and-slow” parallel optical approach, the technology transmits data through hundreds of low-speed optical channels operating simultaneously.

This architecture eliminates the need for several power-hungry components—including DSPs, ADC/DACs, and CDRs—reducing energy consumption to just 1–2 pJ/bit. Overall system power is targeted at roughly 5% of that required by copper-cable solutions. In addition, Micro LED arrays can integrate more than 400 channels within a footprint of less than 1 mm², offering a compact structure, high reliability, and reduced sensitivity to temperature fluctuations.

Although transmission distances are currently limited to less than 10 meters, Micro LED CPO is well suited to scale-up interconnects within AI server racks—a use case that neither copper cables nor silicon-photonics-based CPO can fully address. As a result, the technology has attracted growing interest from global technology leaders and semiconductor companies, triggering a wave of partnerships and ecosystem-building efforts.

Global Players Race to Define the Micro LED CPO Market

The Micro LED CPO industry remains in an early stage, with standardization efforts progressing alongside technical development. Key specifications—including chip dimensions, per-channel data rates, transmission distances, and whether receivers should use photodiodes (PDs) or CMOS sensor arrays—have yet to be finalized.

In this context, competition today centers on influencing future standards, with alliances and resource integration emerging as the preferred strategy. Early participants range from major technology companies such as Microsoft and Marvell to startups including Avicena and Hyperlume.

Microsoft’s MOSAIC architecture exemplifies the “wide-and-slow” philosophy. While a conventional 800Gbps optical link typically consists of eight 100Gbps channels, MOSAIC distributes data across 400 parallel 2Gbps optical channels arranged in a 20×20 array occupying less than 1 mm².

The lower per-channel data rate significantly simplifies signal equalization requirements and eliminates the need for DSPs, ADC/DACs, and CDRs. Power consumption is reduced to 3.1–5.3W, representing a 56–68% improvement over mainstream optical-link solutions. The use of multicore imaging fiber further tackling wiring challenges associated with hundreds of parallel optical channels.

Avicena has taken a different approach with its LightBundle platform, pairing GaN-based Micro LED arrays with PD receivers. Leveraging advanced semiconductor manufacturing processes from TSMC, the solution delivers a baseline bandwidth of 512Gbps, scalable to 896Gbps, while maintaining energy efficiency of 1–2 pJ/bit and stable transmission over distances of up to five meters.

In March 2026, Avicena signed a joint development agreement with ams OSRAM. The partnership is expected to accelerate commercialization by combining LightBundle with ams OSRAM’s mass-production expertise in automotive Micro LED technologies.

Meanwhile, Marvell, a leading supplier of optical networking DSP, has partnered with Mojo Vision in a strategic move to maintain relevance in a future where DSPs may no longer be required in certain optical interconnect architectures.

High-speed connectivity specialist Credo directly acquired Canadian startup Hyperlume in the third quarter of 2025. The company plans to launch a new category of Active Light Cable (ALC) products offering reliability comparable to AEC copper cables while extending transmission distances to 30 meters. Sample shipments are expected in fiscal 2027, followed by volume production ramp-up in fiscal 2028.

While major technology firms and startups have collectively outlined the early framework of the Micro LED CPO ecosystem, significant differences remain in chip specifications, receiver architectures, and system integration approaches. Industry-wide standards are still several years away, making the next two to three years a critical period for specification battles and market positioning.

China’s Emerging Micro LED CPO Ecosystem

Companies in Chinese Mainland and Taiwan have adopted distinct strategies for entering the Micro LED CPO market.

In Chinese mainland, participation has been more diversified. Traditional LED manufacturers are expanding into optical communications, while cross-industry collaborations seek to accelerate technological breakthroughs. Most projects remain in the sample-development and customer-validation stage, though commercialization efforts are steadily advancing.

Companies with active Micro LED CPO initiatives include HC SemiTek, MTC, San’an, Changelight, Chip Foundation, Leyard, Saphlux, Azure, and SmartSens.

Taiwan-based companies, by contrast, are pursuing vertically integrated strategies. Display makers and LED manufacturers are leveraging internal group resources to establish end-to-end supply chains spanning light sources, detectors, and modules before industry standards are finalized.

Among the most notable examples is AUO, which has integrated LED supplier Ennostar and photodiode maker Tyntek into its ecosystem. By adopting a glass-RDL interposer solution, AUO allows customers to deploy Micro LED CPO without investing in their own mass-transfer production lines, largely lowering adoption barriers. The company has already begun system-level CPO validation with international AI and optical communications customers and expects commercialization to progress over the next two to three years.

In late May, AUO also announced a strategic partnership with French Micro LED specialist Aledia to develop next-generation display technologies combining high brightness, low power consumption, and high resolution. The collaboration could eventually expand into optical communications applications.

PlayNitride has entered into cooperation with Brillink, while Innolux is widely viewed as a potential beneficiary of its subsidiary’s electro-optical packaging capabilities, strengthening its vertical integration strategy and competitive positioning.

CPO Reshapes the Value Proposition of Micro LED

Whether through vertical integration in Taiwan, cross-sector partnerships in Chinese mainland, or strategic alliances among overseas technology companies, Micro LED CPO deployments today remain largely focused on sampling and qualification programs. Large-scale shipments have yet to materialize. The key questions for the industry now lie in when market adoption will accelerate, how large the potential could become, and how Micro LED CPO will interact with the broader Micro LED ecosystem.

According to TrendForce, the global market for AI-focused optical transceiver modules is expected to grow from USD 16.5 billion in 2025 to USD 26 billion in 2026, representing annual growth of more than 57%. Modules operating at 800G and above are projected to account for over 60% of the market in 2026, laying a solid foundation for broader CPO adoption.

Against this backdrop, TrendForce forecasts that CPO penetration in AI data center optical modules will rise from approximately 0.5% in 2026 to nearly 35% by 2030.

Shipments of Micro LED CPO optical transceiver modules are expected to begin ramping in the second half of 2028, with the market projected to generate approximately USD 848 million in revenue by 2030.

Beyond enabling more efficient AI data-center interconnects, Micro LED CPO is expected to create meaningful spillover benefits for the display industry. Manufacturing capabilities developed for optical interconnect applications—including ultra-miniaturized Micro LED chips, higher-precision mass transfer processes, and stringent yield-management expertise—are likely to migrate into display production, helping reduce manufacturing costs and accelerate adoption in consumer markets.

Looking ahead, display and optical communication applications are expected to reinforce one another, creating a dual-engine growth model for the Micro LED industry and driving the technology toward large-scale commercialization.

(Photo credit: OSRAM)

As AI-driven memory demand continues to outpace supply, leading Asian memory makers are accelerating capital market strategies to support large-scale expansion. Notably, SK hynix and Kioxia have both advanced plans to issue U.S. depositary receipts (ADRs), underscoring a broader push to tap U.S. investor interest. The following outlines the key developments to date.

Kioxia Targets Spring 2027 ADR Launch

According to Bloomberg, Kioxia is aiming to launch ADRs in spring 2027. Speaking at the company’s annual general meeting last week, CFO Yoshihiko Kawamura said the issuance is planned for April to June, following the close of the current fiscal year at the end of March, as part of efforts to broaden Kioxia’s investor base, the report adds.

The move comes as Kioxia enjoys a remarkable rally in Japan’s equity market. Fueled by the AI investment boom, Kioxia has become one of Japan’s biggest stock market sensations, even surpassing Toyota Motor this month to become Japan’s most valuable listed company.

According to the Chosun Daily, the NAND giant has seen its shares soar 857% this year, reached a JPY 50 trillion market capitalization in a record 18 months after listing, and generated more than JPY 3 trillion in average daily trading value.

Beyond advancing its U.S. ADR plan, Bloomberg reports that Kioxia is examining a potential stock split to improve accessibility for retail investors, as its Tokyo-listed shares—currently among the top performers on the MSCI World Index—continue to trade at elevated levels.

SK hynix Sets July 10 Nasdaq ADR Listing

Separately, SK hynix has disclosed plans to list ADRs representing 17.79 million shares—around 2.5% of its total equity—on the Nasdaq by July 10th, as noted by Maeil Business Newspaper.

The ADR issuance is expected to serve as a key fundraising vehicle, with Yonhap News—citing the Financial Supervisory Service’s electronic disclosure system on the 26th—reporting that the HBM chipmaker plans to raise approximately US$30 billion (around KRW 45 trillion) through the offering.

The report adds that the proceeds will be used for capital expenditures, including construction of the first-phase fab of the Yongin semiconductor cluster, the Cheongju P&T7 advanced packaging facility, and the acquisition of EUV scanner equipment.

Meanwhile, market attention is increasingly focused on the potential inclusion of SK hynix in major global indices following its Nasdaq listing, with analysts cited by Maeli Business Newspaper widely expecting entry into the tech-heavy Nasdaq-100. This stands in contrast to TSMC, which listed on the New York Stock Exchange and was therefore excluded from Nasdaq-100 eligibility, the report says.

Notably, as its South Korean peer SK hynix moves ahead with U.S. capital market plans, interest and inquiries regarding a potential ADR listing for Samsung Electronics have significantly exceeded expectations at a recent overseas investor meeting, Yonhap News reports.

Read more

• [News] Kioxia Adopts Cautious Capex Despite NAND Upcycle: Reportedly 10% Below FY23 Peak, Key Concerns in Focus
• [News] Memory Giants Split on HBM4 Strategy: Samsung HBM4 Sales Reportedly Tops $1B, SK hynix Slows Ramp

(Photo credit: SK hynix)

As Micron noted in its earnings call that tight market conditions are likely to persist beyond 2027, Lenovo is taking a more cautious stance. Wccftech, citing company management, reports that Lenovo sees higher memory pricing as potentially settling into a “new normal” well into 2030 and beyond.

The report, citing Computer Base, notes that at ISC 2026 in Germany, Lenovo presented a slide outlining the current pricing trajectory of DRAM and NAND, highlighting a sharp and sustained upswing across the memory market. According to Lenovo, prices began to accelerate rapidly around late Q3 to early Q4 2025, and have since climbed to levels widely considered unprecedented.

As a result, memory prices are not expected to revert to earlier levels seen in early 2025, or the more normalized pricing environment that preceded the recent surge, the report adds.

Notably, Lenovo’s outlook already assumes that significant new capacity will come online starting around 2028, suggesting supply additions may not be sufficient to reverse the current pricing cycle, Computer Base points out.

The view broadly aligns with remarks from SK hynix Chairman Chey Tae-won, who has previously indicated that supply-demand tightness could persist through 2030, according to TechNews. Against this backdrop, SK hynix is said to be targeting a doubling of wafer capacity by 2030 and a tripling by 2034.

Read more

• [News] Lenovo Reportedly Set for July Price Hikes Across Product Portfolio as Memory Costs Pressure PC Market
• [News] SK hynix Advances DRAM and NAND Roadmap, Targets 3x Wafer Output by 2034, 375-Layer NAND at Year-End

(Photo credit: Lenovo)